USB2224 datasheet(13/20 Pages) SMSC

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Bus Powered USB2.0 Flash Media Controller

Datasheet

SMSC USB2224

Page 13

Revision 1.3 (06-13-06)

DATASHEET

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

Memory

Address Bus

MA[15:0]

These signals address memory locations within the

external memory.

Memory Read

Strobe

nMWR

Program Memory Write; active low

Memory Read

Strobe

nMRD

Program Memory Read; active low

Memory Chip

Enable

nMCE

Program Memory Chip Enable; active low. This signal is

asserted, when the device is not is SUSPEND mode.

Note: This signal is held in a logic ‘high’ state (inactive)

during nRESET assertion.

MISC

GPIO6,

ROMEN and

RXD

GPIO6

/ROMEN

I/O8PU

This pin has an internal weak pullup resistor that can be

enabled or disabled by the state of nRESET.

The pullup is enabled when nRESET is active.

The pullup is disabled, when the nRESET is inactive

(some clock cycles later, after the rising edge of

nRESET).

The state of this pin is latched internally on the rising

edge of nRESET to determine if internal or external

program memory is used.

The state latched is stored in ROMEN bit of GPIO_IN1

used as GPIO6 or RXD.

When pulled low via an external weak pulldown resistor,

an external program memory should be connected to the

memory data bus. The USB2224 uses this external bus

for program execution.

When this pin is left unconnected or pulled high by a

weak pullup resistor, the USB2224 uses the internal ROM

for program execution.

This pin’s function while operating from internal ROM is

shown in Table 6.3 - GPIO Usage.

General

Purpose I/O

GPIO1

I/O8

This pin may be used either as input, edge sensitive

interrupt input, or output.

This pin’s function while operating from internal ROM is

shown in Table 6.3 - GPIO Usage.

General

Purpose I/O

GPIO2

I/O8

This pin may be used either as input, edge sensitive

interrupt input, or output.

This pin’s function while operating from internal ROM is

shown in Table 6.3 - GPIO Usage.

General

Purpose I/O

GPIO3

I/O8

This pin may be used either as input, edge sensitive

interrupt input, or output.

This pin’s function while operating from internal ROM is

shown in Table 6.3 - GPIO Usage.

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