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USB3290 Scheda tecnica(PDF) 38 Page - SMSC Corporation

Il numero della parte USB3290
Spiegazioni elettronici  Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
PDF  43 Pages
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Produttore elettronici  SMSC [SMSC Corporation]
Homepage  http://www.smsc.com
Logo SMSC - SMSC Corporation

USB3290 Scheda tecnica(HTML) 38 Page - SMSC Corporation

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Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
Revision 1.2 (10-27-06)
38
SMSC USB3290
DATASHEET
8.11
Assertion of Resume
In this case, an event internal to the device initiates the resume process. A device with remote wake-
up capability must wait for at least 5ms after the bus is in the idle state before sending the remote
wake-up resume signaling. This allows the hubs to get into their suspend state and prepare for
propagating resume signaling.
The device has 10ms where it can draw a non-suspend current before it must drive resume signaling.
At the beginning of this period the SIE may negate SUSPENDN, allowing the transceiver (and its
oscillator) to power up and stabilize.
Figure 8.7 illustrates the behavior of a device returning to HS mode after being suspended. At T4, a
device that was previously in FS mode would maintain TERMSELECT and XCVRSELECT high.
To generate resume signaling (FS 'K') the device is placed in the "Disable Bit Stuffing and NRZI
encoding" Operational Mode (OPMODE [1:0] = 10), TERMSELECT and XCVRSELECT must be in FS
mode, TXVALID asserted, and all 0's data is presented on the DATA bus for at least 1ms (T1 - T2).
Figure 8.7 Resume Timing Behavior (HS Mode)
Table 8.9 Resume Timing Values (HS Mode)
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
Internal device event initiating the resume
process
0 (reference)
T1
Device asserts FS 'K' on the bus to signal
resume request to downstream port
T0 < T1 < T0 + 10ms.
T2
The device releases FS 'K' on the bus. However
by this time the 'K' state is held by downstream
port.
T1 + 1.0ms < T2 < T1 + 15ms
T3
Downstream port asserts SE0.
T1 + 20ms
T4
Latest time at which a device, which was
previously in HS mode, must restore HS mode
after bus activity stops.
T3 + 1.33µs {2 Low-speed bit times}



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