USB3500 datasheet(40/46 Pages) SMSC

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Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

Revision 1.0 (04-04-05)

SMSC USB3500

DATASHEET

To detect the assertion of the downstream Chirp K's and Chirp J's for 2.5us {TFILT}, the Link must see

the appropriate LINESTATE signals asserted continuously for 165 CLKOUT cycles.

7.11

Assertion of Resume

In this case, an event internal to the device initiates the resume process. A device with remote wake-

up capability must wait for at least 5ms after the bus is in the idle state before sending the remote

wake-up resume signaling. This allows the hubs to get into their suspend state and prepare for

propagating resume signaling.

The device has 10ms where it can draw a non-suspend current before it must drive resume signaling.

At the beginning of this period the Link may negate SUSPENDN, allowing the transceiver (and its

oscillator) to power up and stabilize.

Figure 7.7 illustrates the behavior of a device returning to HS mode after being suspended. At T4, a

device that was previously in FS mode would maintain TERMSELECT and XCVRSELECT high.

To generate resume signaling (FS 'K') the device is placed in the “Disable Bit Stuffing and NRZI

encoding” Operational Mode (OPMODE [1:0] = 10), TERMSELECT and XCVRSELECT must be in FS

mode, TXVALID asserted, and all 0's data is presented on the DATA bus for at least 1ms (T1 - T2).

Table 7.9 HS Detection Handshake Timing Values from Suspend

TIMING

PARAMETER

DESCRIPTION

VALUE

While in suspend state an SE0 is detected on the USB. HS

Handshake begins. D+ pull-up enabled, HS terminations

disabled, SUSPENDN negated.

0 (HS Reset T0)

First transition of CLKOUT. CLKOUT “Usable” (frequency

accurate to ±10%, duty cycle accurate to 50±5).

T0 < T1 < T0 + 5.6ms

Device asserts Chirp K on the bus.

T1 < T2 < T0 + 5.8ms

Device removes Chirp K from the bus. (1 ms minimum width)

and begins looking for host chirps.

T2 + 1.0 ms < T3 <

T0 + 7.0 ms

CLK “Nominal” (CLKOUT is frequency accurate to ±500 ppm,

duty cycle accurate to 50±5).

T1 < T3 < T0 + 20.0ms

Figure 7.7 Resume Timing Behavior (HS Mode)

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