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HC5523IP Scheda tecnica(PDF) 21 Page - Intersil Corporation

Il numero della parte HC5523IP
Spiegazioni elettronici  LSSGR/TR57 CO/Loop Carrier SLIC with Low Power Standby
PDF  22 Pages
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Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HC5523IP Scheda tecnica(HTML) 21 Page - Intersil Corporation

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21
HC5523
Plastic Leaded Chip Carrier Packages (PLCC)
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane
contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
-C-
A1
A
SEATING
PLANE
0.020 (0.51)
MIN
VIEW “A”
D2/E2
0.025 (0.64)
0.045 (1.14)
R
0.042 (1.07)
0.056 (1.42)
0.050 (1.27) TP
E
E1
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
C
L
D1
D
0.020 (0.51) MAX
3 PLCS
0.026 (0.66)
0.032 (0.81)
0.045 (1.14)
MIN
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
VIEW “A” TYP.
0.004 (0.10)
C
-C-
D2/E2
C
L
N28.45 (JEDEC MS-018AB ISSUE A)
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.165
0.180
4.20
4.57
-
A1
0.090
0.120
2.29
3.04
-
D
0.485
0.495
12.32
12.57
-
D1
0.450
0.456
11.43
11.58
3
D2
0.191
0.219
4.86
5.56
4, 5
E
0.485
0.495
12.32
12.57
-
E1
0.450
0.456
11.43
11.58
3
E2
0.191
0.219
4.86
5.56
4, 5
N28
28
6
Rev. 2 11/97



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