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CIRCC Scheda tecnica(PDF) 23 Page - SMSC Corporation |
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CIRCC Scheda tecnica(HTML) 23 Page - SMSC Corporation |
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23 / 70 page ![]() 23 SCE CONTROLS The CIrCC SCE Registers are arranged in 7-byte blocks. Of the eight possible register blocks, four are used in this implementation. The Master Block Control Register controls access to the register blocks. Table 13 lists all of the SCE registers in all blocks. Table 13 - SCE Register Addressing BLOCK ADDRESS DIRECTION REGISTER NAME X 7 R/W Master Block Control 0 0 R/W Data Register 0 1 RO Interrupt Identification 0 2 R/W Interrupt Enable 0 3 RO Line Status (read) 0 3 WO Line Status Address (write) 0 4 R/W Line Control A 0 5 R/W Line Control B 0 6 R/W Bus Status 1 0 R/W SCE Configuration A 1 1 R/W SCE Configuration B 1 2 R/W FIFO Threshold 1 3 RO FIFO COUNT 1 6 R/W SCE Configuration C 2 0 R/W Consumer IR Control 2 1 R/W Consumer IR Carrier Rate 2 2 R/W Consumer IR Bit Rate 2 3 R/W Custom Code 2 4 R/W Custom Code 2 5 R/W Data Code 3 0 RO SMSC ID (high) 3 1 RO SMSC ID (low) 3 2 RO CHIP ID 3 3 RO VERSION Number 3 4 RO IRQ Level DMA Channel 3 5 RO Software Select A 3 6 RO Software Select B |
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