AM29SL400D datasheet(17/41 Pages) AMD

17 / 41 page

April 13, 2005 Rev. A Amend. +1

Am29SL400D

ADV ANCE

I N FO RMAT I O N

Operations, on page 29 for parameters, and to

Figure 17, on page 30 for timing diagrams.

Note: See Table 5 on page 17 for program command

sequence.

Figure 3.

Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does

not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 5 on

page 17 shows the address and data requirements for

the chip erase command sequence.

Any c o m mand s w r i tten to th e c h ip du r ing th e

Embedded Erase algorithm are ignored. Note that a

hardware reset during the chip erase operation imme-

diately terminates the operation. The Chip Erase

command sequence should be reinitiated once the

device has returned to reading array data, to ensure

data integrity.

The system can determine the status of the erase oper-

ation by using DQ7, DQ6, DQ2, or RY/BY#. See

Write

Operation Status, on page 18 for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data and

addresses are no longer latched.

Figure 4, on page 16 illustrates the algorithm for the

eras e oper ation. See the

Eras e/Prog r a m

Operations, on page 29 for parameters, and to

Figure 18, on page 31 for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 5 on page 17 shows the

address and data requirements for the sector erase

command sequence.

The device does

not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of

sectors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Eras e

Suspend during the time-out period resets the

device to reading array data. The system must

rewrite the command sequence and any additional

sector addresses and commands.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See

DQ3: Sector Erase

Timer, on page 20.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

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