LTC7825AVPBF datasheet(14/19 Pages) AD

14 / 19 page

LTC7825

Rev. A

For more information www.analog.com

DESIGN EXAMPLE

As a design example using LTC7825 in a voltage divider

application, assumes VIN = 12V ~ 20V, VOUT = 6V ~ 10V,

IOUT = 10A.

The switching frequency selection is a trade-off between

switching losses and solution size. High switching fre-

quency generates high switching losses but may require

fewer flying capacitors and output capacitors. In most

applications, the best switching frequency is around

300kHz to 600kHz, therefore 500kHz is a good starting

point. Select the flying capacitors so that the ripple voltage

at the flying capacitor is around 100mV at the full-load

condition (see Equation 1).

CFLY =

IOUT

2• fSW •CFLY_RIPPLE

10A

2•500kHz •100mV

= 100µF

(1)

Considering the ceramic capacitance derating at 10V

DC bias voltage, twelve 10μF/X7R capacitors are paral-

leled as the flying capacitors. The worst-case RMS cur-

rent may be 40% higher than the maximum output cur-

rent. The worst-case RMS current on each capacitor is

10A • 140%/12 = 1.17A. Double check and make sure the

RMS current on each capacitor is below the ripple current

ratings and temperature rise is below the limits.

The input/output capacitor selection is similar to the fly-

ing capacitor selection. More output capacitors result

in smaller output voltage ripple and higher efficiency.

Because of the lower RMS current, the output capacitor

value can be much less than the flying capacitor. In gen-

eral, start with half the number of the flying capacitors as

the input/output capacitors. The input capacitors can be

placed from VHIGH to PGND or may be connected between

VHIGH and VLOW to serve as input/output capacitors at the

same time. However, the voltage rating of those capacitors

must be selected based on the input voltage instead of

the output voltage.

The design example is shown in Figure 3 in the Typical

Applications section. By running experimental tests, the

full-load efficiency is almost the same at 500kHz and

600kHz switching frequency. Tie FREQ pin to INTVCC for

600kHz operation. At 10A load, the VLOW is 250mV to

300mV lower than VHIGH/2, taking into account the ripple

on the VLOW, the HYS_PGRM pin is connected to INTVCC

to program a 400mV hysteresis window.

APPLICATIONS INFORMATION

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