21

FN6140.2

June 15, 2006

FIGURE 28. MODE 1 (STROBED OUTPUT)

FIGURE 29. MODE 2 (BIDIRECTIONAL)

NOTE:

Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF

• MASK • STB • RD + OBF • MASK

• ACK • WR)

tWOB (21)

tWB (12)

tAK (15)

tAIT (27)

tAOB (22)

tWIT

OBF

WR

INTR

ACK

OUTPUT

(28)

tWOB

tAOB

tAK

tAD (19)

tKD

tPH (18)

tPS (17)

tSIB

tST

OBF

WR

INTR

ACK

IBF

STB

PERIPHERAL

BUS

RD

tRIB (24)

DATA FROM

PERIPHERAL TO 82C55A

DATA FROM

82C55A TO PERIPHERAL

DATA FROM

82C55A TO CPU

DATA FROM

CPU TO 82C55A

(21)

(22)

(15)

(16)

(20)

(23)

(NOTE)

(NOTE)

MS82C55A, MQ82C55A, MP82C55A