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TMS320C6421 Scheda tecnica(PDF) 1 Page - Texas Instruments |
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TMS320C6421 Scheda tecnica(HTML) 1 Page - Texas Instruments |
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1 / 227 page  www.ti.com 1 TMS320C6421 Fixed-Point Digital Signal Processor 1.1 Features TMS320C6421 Fixed-Point Digital Signal Processor SPRS346B – JANUARY 2007 – REVISED APRIL 2007 • C64x+ L1/L2 Memory Architecture • High-Performance Digital Signal Processor (C6421) – 128K-Bit (16K-Byte) L1P Program RAM/Cache [Flexible Allocation] – 2.5-, 2.-, 1.67-ns Instruction Cycle Time – 128K-Bit (16K-Byte) L1D Data RAM/Cache – 400-, 500-, 600-MHz C64x+™ Clock Rate [Flexible Allocation] – Eight 32-Bit C64x+ Instructions/Cycle – 512K-Bit (64K-Byte) L2 Unified Mapped – 3200, 4000, 4800 MIPS RAM/Cache [Flexible Allocation] – Fully Software-Compatible With C64x • Endianess: Supports Both Little Endian and – Commercial and Extended Temperature Big Endian Ranges • External Memory Interfaces (EMIFs) • VelociTI.2™ Extensions to VelociTI™ – 16-Bit DDR2 SDRAM Memory Controller Advanced Very-Long-Instruction-Word (VLIW) With 128M-Byte Address Space (1.8-V I/O) TMS320C64x+™ DSP Core – Asynchronous 8-Bit-Wide EMIF (EMIFA) – Eight Highly Independent Functional Units With up to 64M-Byte Address Reach With VelociTI.2 Extensions: • Flash Memory Interfaces • Six ALUs (32-/40-Bit), Each Supports • NOR (8-Bit-Wide Data) Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle • NAND (8-Bit-Wide Data) • Two Multipliers Support Four 16 x 16-Bit • Enhanced Direct-Memory-Access (EDMA) Multiplies (32-Bit Results) per Clock Controller (64 Independent Channels) Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • Two 64-Bit General-Purpose Timers (Each Results) per Clock Cycle Configurable as Two 32-Bit Timers) – Load-Store Architecture With Non-Aligned • One 64-Bit Watch Dog Timer Support – 64 32-Bit General-Purpose Registers • One UART With RTS and CTS Flow Control – Instruction Packing Reduces Code Size • Master/Slave Inter-Integrated Circuit – All Instructions Conditional (I2C Bus™) – Additional C64x+™ Enhancements • Multichannel Buffered Serial Port (McBSP0) • Protected Mode Operation – I2S and TDM • Exceptions Support for Error Detection – AC97 Audio Codec Interface and Program Redirection – SPI • Hardware Support for Modulo Loop – Standard Voice Codec Interface (AIC12) Auto-Focus Module Operation – Telecom Interfaces – ST-Bus, H-100 • C64x+ Instruction Set Features – 128 Channel Mode – Byte-Addressable (8-/16-/32-/64-Bit Data) • Multichannel Audio Serial Port (McASP0) – 8-Bit Overflow Protection – Four Serializers and SPDIF (DIT) Mode – Bit-Field Extract, Set, Clear • 16-Bit Host-Port Interface (HPI) – Normalization, Saturation, Bit-Counting • 10/100 Mb/s Ethernet MAC (EMAC) – VelociTI.2 Increased Orthogonality – IEEE 802.3 Compliant – C64x+ Extensions – Supports Multiple Media Independent • Compact 16-bit Instructions Interfaces (MII, RMII) • Additional Instructions to Support – Management Data I/O (MDIO) Module Complex Multiplies Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the Copyright © 2007–2007, Texas Instruments Incorporated formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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