AS4SD16M16 datasheet(3/51 Pages) AUSTIN

3 / 51 page

SDRAM

AS4SD16M16

Austin Semiconductor, Inc.

AS4SD16M16

Rev. 1.0 11/02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

PIN NUMBER

SYMBOL

TYPE

DESCRIPTION

CLK

Input

Clock: CLK is driven by the system clock. All SDRAM input

signals are sampled on the positive edge of CLK. CLK also

increments the internal burst counter and controls the output

registers.

CKE

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the

CLK signal. Deactivating the clock provides PRECHARGE

POWER-DOWN and SLEF REFRESH operation (all banks idle),

ACTIVE POWER-DOWN (row active in any bank) or CLOCK

SUSPEND operation (burst/access in progress). CKE is

synchronous except after the device enters power-down and self

refresh modes, where CKE becomes asynchronous until after

exiting the same mode. The input buffers, including CLK, are

disabled during power-down and self refresh modes, providing low

standby power. CKE may be tied HIGH.

CS\

Input

Chip Select: CS\ enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are

masked when CS\ is registered HIGH. CS\ provides for external

bank selection on systems with multiple banks. CS\ in considered

part of the command code.

16, 17, 18

WE\, CAS\,

RAS\

Input

Command Inputs: WE\, CAS\ and RAS\ (along with CS\) define

the command being entered.

15, 39

DQML, DQMU

Input

Input/Output Mask: DQM is an input mask signal for write

accesses and an output enable signal for read accesses. Input

data is masked when DWM is sampled HIGH during a WRITE

cycle. The outptu buffers are placed in a High-Z state (two-clock

latency) when DQM is sampled HIGH during a READ cycle.

DQML corresponds to DQ0-DQ7 and DQMH corresponds to

DQ8-DQ15. DQML and DQMH are considered same state when

referenced as DQM.

20, 21

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank the

ACTIVE, READ, WRITE, or PRECHARGE command is being

applied.

23-26, 29-34, 22, 35, 36

A0 - A12

Input

Address Inputs: A0-A12 are sampled during the ACTIVE

command (row address A0-A12) and READ/WRITE command

(column-address A0-A8; with A10 defining auto precharge) to

select one location out of the memory array in the respective

bank. A10 is sampled during a PRECHARGE command to

determine if all banks are to be prechaged (A10 [HIGH]) or bank

selected by (A10 [LOW]). The address inputs also provide the

op-code during LOAD MODE REGISTER COMMAND.

2, 4, 5, 7, 8, 10, 11, 13, 42,

44, 45, 47, 48, 50, 51, 53

DQ0 - DQ15

I/O

Data Input/Output: Data bus

---

No Connect: This pin should be left unconnected.

3, 9, 43, 49

VDDQ

Supply

DQ Power: Isolated DQ power to the die for improved noise

immunity.

6, 12, 46, 52

VSSQ

Supply

DQ Ground: Isolated DQ ground to the die for imporved noise

immunity.

1, 14, 27

VDD

Supply Power Supply: +3.3V ±0.3V

28, 41, 54

VSS

Supply Ground

PIN DESCRIPTIONS

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