SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

PIN DESCRIPTIONS (continued)

TQFP PINS

SYMBOL

TYPE

DESCRIPTION

64

ZZ

Input

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a

low-power standby mode in which all data in the memory array is retained. When ZZ

is active, all other inputs are ignored.

89

CLK

Input

Clock: This signal registers the address, data, chip enables, byte write enables and

burst control inputs on its rising edge. All synchronous inputs must meet setup and

hold times around the clock's rising edge.

98, 92

CE\, CE2\

Input

Synchronous Chip Enable: These active LOW inputs are used to enable the device

and are sampled only when a new external address is loaded (ADV/LD\ LOW). CE2\

can be used for memory depth expansion.

97

CE2

Input

Synchronous Enable: This active HIGH input is used to enable the device and is

sampled only when a new external address is loaded (ADV/LD\ LOW). This input can

be used for memory depth expansion.

86

OE\

(G\)

Input

Output Enable: This active LOW, asynchronous inputs enables the data I/O output

drivers. G\ is the JEDEC-standard term for OE\.

85

ADV/LD\

Input

Synchronous Address Advance/Load: When HIGH, this input is used to advance the

internal burst counter, controlling burst access after the external address is loaded.

When ADV/LD\ is HIGH, R/W\ is ignored. A LOW on ADV/LD\ clocks a new address

at the CLK rising edge.

31

MODE

(LBO\)

Input

Mode: This inputs selects the burst sequence. A LOW on this pin selects linear burst.

NC or HIGH on this pin selects interleaved burst. Do not alter input state while device

is operating. LBO\ is the JEDEC-standard term for MODE.

(a) 51, 52, 53, 56-59,

62, 63

(b) 68, 69, 72-75, 78,

79, 80

(c)1, 2, 3, 6-9, 12, 13

(d) 18, 19, 22-25, 28,

29, 30

DQa

DQb

DQc

DQd

Input/Output SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins;

Byte "d" is DQd pins. Input data must meet setup and hold times around the rising

edge CLK.

15, 16, 41, 65, 91

Supply

Power Supply: See DC Electrical Characteristics and Operating Conditions for range.

5, 10, 14, 17, 21, 26

40, 55, 60, 66, 67, 71

76, 90

Vss

Ground

Ground: GND

4, 11, 20, 27, 54, 61

70, 77

Supply

Isolated Output Buffer Supply:

See DC Electrical Characteristics and Operating

Conditions for range.

38, 39, 42, 43, 83, 84

64

NC

----

No Connect: These pins can be left floating or connected to GND to minimize thermal

impedance.

38, 39, 42, 43

DNU

----

Do Not Use: These signals may with be unconnected or wired to GND to

minimize thermal impedance.

83, 84

NF

----

No Function: These pins are internally connected to the die and will have the

capacitance of an input pin. It is allowable to leave these pins unconnected or

driven by signals. Pins 83 and 84 are reserved for address expansion.