AS5SS256K18

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

SSRAM

AS5SS256K18

Austin Semiconductor, Inc.

INTERLEAVED BURST ADDRESS TABLE (MODE=NC OR HIGH)

LINEAR BURST ADDRESS TABLE (MODE=LOW)

FUNCTIONAL BLOCK DIAGRAM

NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing

diagrams for detailed information.

18

18

16

18

SA0, SA1, SA

MODE

ADV\

CLK

ADSC\

ADSP\

BWb\

BWa\

BWE\

GW\

CE\

CE2

CE2\

OE\

2

ADDRESS

REGISTER

BINARY

COUNTER AND

LOGIC

BYTE "b"

WRITE REGISTER

BYTE "a"

WRITE REGISTER

ENABLE

REGISTER

CLR

Q1

Q0

SA1'

SA0'

INPUT

REGISTERS

OUTPUT

BUFFERS

SENSE

AMPS

256K x 9 x 2

MEMORY

ARRAY

9

9

BYTE "b"

WRITE DRIVER

BYTE "a"

WRITE DRIVER

9

9

18

18

18

18

DQs

DQPa

DQPb

2

SA0-SA1

FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X…X00

X…X01

X…X10

X…X11

X…X01

X…X00

X…X11

X…X10

X…X10

X…X11

X…X00

X…X01

X…X11

X…X10

X…X01

X…X00

FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X…X00

X…X01

X…X10

X…X11

X…X01

X…X10

X…X11

X…X00

X…X10

X…X11

X…X00

X…X01

X…X11

X…X00

X…X01

X…X10

PARTIAL TRUTH TABLE FOR WRITE COMMANDS

FUNCTION

GW\

BWE\

BWa\

BWb\

READ

H

H

X

X

READ

H

L

H

H

WRITE Byte "a"

H

L

L

H

WRITE Byte "b"

H

L

H

L

WRITE All Bytes

H

L

L

L

WRITE All Bytes

L

X

X

X

NOTE: Using BWE\ and BWa\ through BWb\, any one or more bytes may be

written.