DRAM

DRAM

DRAM

DRAM

DRAM

MT4C4001J

Austin Semiconductor, Inc.

MT4C4001J

Rev. 1.5 10/02

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

2

GENERAL DESCRIPTION (cont.)

cycle is always initiated with a row address strobe-in by RAS\

followed by a column address strobed-in by CAS\. CAS\ may

be toggled-in by holding RAS\ LOW and strobing-in different

column addresses, thus executing faster memory cycles.

Returning RAS\ HIGH terminates the FAST PAGE MODE

operation.

Returning RAS\ and CAS\ HIGH terminates a memory cycle

and decreases chip current to a reduced standby level. Also,

the chip is preconditioned for the next cycle during the RAS\

HIGH time. Memory cell data is retained in its corrected

stated by maintaining power and executing any RAS\ cycle

(READ, WRITE, RAS\-ONLY, CAS\-BEFORE-RAS\, or

HIDDEN REFRESH) so that all 1,024 combinations of RAS\

addresses (A0-A9) are executed at least every 16ms,

regardless of sequence. The CBR REFRESH cycle will

invoke the internal refresh counter for automatic RAS\

addressing.

FUNCTIONAL BLOCK DIAGRAM

FAST PAGE MODE

WE\

DQ1

CAS\

DQ2

DQ3

DQ4

OE\

Vcc

A0

Vss

A1

A2

A3

A4

A5

A6

A7

A8

A9

RAS\

NO. 2 CLOCK

GENERATOR

NO. 1 CLOCK

GENERATOR

COLUMN

ADDRESS

BUFFER

REFRESH

CONTROLLER

REFRESH

COUNTER

ROW ADDRESS

BUFFERS (10)

*EARLY-WRITE

DETECTION CIRCUIT

DATA IN

BUFFER

DATA OUT

BUFFER

COLUMN

DECODER

SENSE AMPLIFIERS

I/O GATING

MEMORY

ARRAY

1024

1024 x 4

1024

4

4

4

4

10

10

10

10

10

NOTE: WE\ LOW prior to CAS\ LOW, EW detection circuit output is a HIGH (EARLY-WRITE)

CAS\ LOW prior to WE\ LOW, EW detection circuit output is a LOW (LATE-WRITE)