PCD8544 datasheet(20/32 Pages) PHILIPS

20 / 32 page

1999 Apr 12

Philips Semiconductors

Product speciﬁcation

× 84 pixels matrix LCD controller/driver

PCD8544

12 AC CHARACTERISTICS

Notes

2. RES may be LOW before VDD goes HIGH.

3. th5 is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE

(see Fig.15).

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fOSC

oscillator frequency

kHz

fclk(ext)

external clock frequency

100

kHz

fframe

frame frequency

fOSC or fclk(ext) = 32 kHz; note 1

−

tVHRL

VDD to RES LOW

Fig.16

0(2)

−

tWL(RES)

RES LOW pulse width

Fig.16

100

−−

Serial bus timing characteristics

fSCLK

clock frequency

VDD = 3.0 V ±10%

−

4.00

MHz

Tcy

clock cycle SCLK

All signal timing is based on

20% to 80% of VDD and

maximum rise and fall times of

10 ns

250

−−

tWH1

SCLK pulse width HIGH

100

−−

tWL1

SCLK pulse width LOW

100

−−

tsu2

SCE set-up time

−−

th2

SCE hold time

100

−−

tWH2

SCE min. HIGH time

100

−−

th5

SCE start hold time; note 3

100

−−

tsu3

D/C set-up time

100

−−

th3

D/C hold time

100

−−

tsu4

SDIN set-up time

100

−−

th4

SDIN hold time

100

−−

frame

clk ext

()

480

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