PCF5083HSLASH001SLASHF2 datasheet(108/136 Pages) PHILIPS

108 / 136 page

1996 Oct 29

108

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

Table 90 Audio Interface Conﬁguration Register

Note

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

Table 91 IOM®-2 Interface Interrupt Flag Register

Notes

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

2. These flags change from ‘0’ to ‘1’ after the IOM®-2 interface was enabled with CLOCK_MODE = 0 and

MASTERx_EN = ‘0’ after the state machined of the monitor/CI master units are in an initial state.

BIT

R/W

SYMBOL

OPERATION (if bit is set)

RST = 0

RSTx=0(1)

R/W

TX_EN

Set to a logic 1 to enable the Voice Port transmit

section

−

R/W

TX_DEST

Select Voice Port transmit section data port

−

R/W

RX_EN

Set to a logic 1 to enable the Voice Port receive section

−

R/W

RX_SOURCE

Select Voice Port receive section data port

−

R/W

TX_SLOT0

Select IOM®-2 timeslot for the Voice Port transmit

section

−

R/W

TX_SLOT1

−

R/W

TX_SLOT2

−

R/W

TX_SLOT3

−

R/W

RX_SLOT0

Select IOM®-2 timeslot for the Voice Port receive

section

−

R/W

RX_SLOT1

−

R/W

RX_SLOT2

−

R/W

RX_SLOT3

−

R/W

TRANS_EN

Set to a logic 1 to enable the Voice Port transparent

mode

−

BIT

R/W

SYMBOL

OPERATION (if bit is set)

RST = 0

RSTx=0(1)

MON0_IBF

Monitor master 0 input buffer full

−

MON0_OBE(2)

Monitor master 0 output buffer empty

0(1)

−

MON1_IBF

Monitor master 1 input buffer full

−

MON1_OBE(2)

Monitor master 1 output buffer empty

0(1)

−

CI0_IBF

C/I channel master 0 input buffer full

−

CI0_OBE(2)

C/I channel master 0 output buffer empty

0(1)

−

CI1_IBF

C/I channel master 1 input buffer full

−

CI1_OBE(2)

C/I channel master 1 output buffer empty

0(1)

−

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