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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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PCK2020DL Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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PCK2020DL Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
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10 / 16 page  Philips Semiconductors Product specification PCK2020 CK00 (100/133MHz) spread spectrum differential system clock generator 2000 Nov 13 10 PCI OUTPUTS SYMBOL PARAMETER LIMITS Tamb = 0°C to +70°C UNITS NOTES SYMBOL PARAMETER 133 MHz MODE 100 MHz MODE UNITS NOTES MIN MAX MIN MAX TPKP PCI period 30.0 N/A 30.0 N/A ns 2, 3, 9, 20 TPKH PCI HIGH time 12.0 N/A 12.0 N/A ns 5, 10, 20 TPKL PCI LOW time 12.0 N/A 12.0 N/A ns 6, 10, 20 TRISE PCI rise time 0.5 2.0 0.5 2.0 ns 8, 20 TFALL PCI fall time 0.5 2.0 0.5 2.0 ns 8, 20 TJITTER Cycle-to-cycle jitter 500 500 ps 18, 20 DUTY CYCLE Output Duty Cycle 45 55 45 55 % 18, 20 TSKEW Pin-to-pin skew 500 500 ps 18, 20 USB CLOCK OUTPUT, 48 MHz (LUMP CAPACITANCE TEST LOAD = 20 pF) SYMBOL PARAMETER LIMITS Tamb = 0°C to +70°C UNITS NOTES SYMBOL PARAMETER 48 MHz UNITS NOTES MIN MAX MIN MAX f Frequency, Actual 48.008 MHz fD Deviation from 48 MHz +167 ppm THKL 3V48MHZCLK LOW time 5.05 N/A 5.05 N/A ns 20 TRISE 3V48MHZCLK rise time 1.0 4.0 1.0 4.0 ns 8, 20 TFALL 3V48MHZCLK fall time 1.0 4.0 1.0 4.0 ns 8, 20 TJITTER Cycle-to-cycle jitter 350 350 ps 18, 20 DUTY CYCLE Output Duty Cycle 45 55 45 55 % 18, 20 REF CLOCK OUTPUT, (LUMP CAPACITANCE TEST LOAD = 20 pF) SYMBOL PARAMETER LIMITS Tamb = 0°C to +70°C UNITS NOTES SYMBOL PARAMETER 48 MHz UNITS NOTES MIN MAX MIN MAX f Frequency, Actual 14.318 MHz 20 THKL REF CLK LOW time 31.0 36.67 31.0 36.67 ns 20 THKH REF CLK HIGH time 32.0 37.5 32.0 37.5 ns 20 TRISE REF CLK rise time N/A N/A N/A N/A ns 8, 20 TFALL REF CLK fall time N/A N/A N/A N/A ns 8, 20 TJITTER Cycle-to-cycle jitter 1000 1000 ps 18, 20 DUTY CYCLE Output Duty Cycle 45 55 45 55 % 18, 20 ALL OUTPUTS SYMBOL PARAMETER LIMITS Tamb = 0°C to +70°C UNITS NOTES SYMBOL PARAMETER 133 MHz MODE 100 MHz MODE UNITS NOTES MIN MAX MIN MAX TpZL, tpZH Output enable delay (all outputs) 1.0 10.0 1.0 10.0 ns 20 TpLZ, tpZH Output disable delay (all outputs) 1.0 10.0 1.0 10.0 ns 20 TSTABLE All clock Stabilization from Power-up 3 3 ms 7, 20 |
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