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LTP8800-4AIPVPBF Scheda tecnica(PDF) 10 Page - Analog Devices

Il numero della parte LTP8800-4AIPVPBF
Spiegazioni elettronici  200A DC/DC μModule Regulator with PMBus Interface
PDF  21 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

LTP8800-4AIPVPBF Scheda tecnica(HTML) 10 Page - Analog Devices

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LTP8800-4A
10
Rev. A
For more information www.analog.com
PolyPhase CONFIGURATION
When configuring a PolyPhase® rail with multiple
LTP8800-4A, the user must share the SYNC and ISHARE
pins. An external clock source at the desired switching
frequency is required for current sharing applications. The
internal digital phase-locked loop is capable of determine
the frequency on the SYNC pin and locking the internal
switching frequency to the external frequency. The lock
or capture range is ±10% of the switching frequency
APPLICATIONS INFORMATION
(Register 0x33). The relative phasing of all the channels
should be spaced equally. This can be configured using
Register 0x37. A phase shift in steps of 22.5 degree can
be added.
PolyPhase LOAD SHARING
Multiple LTP8800-4A can be arrayed in order to provide a
balanced load-share solution by bussing the ISHARE pins.
Figure 4 illustrates a 2-phase design sharing connections
required for load sharing.
VIN
SYNC
CTRL
SMBALERT
SDA
SCL
ISHARE
VS–
VS+
VOUT
4.7µF
LTP8800-4A
7V0
3V3
VIN
45V TO 65V
7V
3V3
2.00k
100pF
100µF
×16
560µF
×16
PMBus
ISHARE BUS
550kHz CLK
VIN
SYNC
CTRL
SMBALERT
SDA
SCL
ISHARE
VS+
VOUT
4.7µF
LTP8800-4A
88004a F04
7V0
3V3
VIN
45V TO 65V
7V
3V3
PMBus
ISHARE BUS
550kHz CLK
210Ω
ADD
750Ω
ADD
GND
GND
1.00k
7.5Ω
VS–
2.00k
100pF
1.00k
7.5Ω
VOUT 0.75V 400A
Figure 4. 2-Phase Operation Producing 0.75V at 400A



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