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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 70

Address: 0x0E

Default Value: 0x30

Access: Read/Write

Bit

Bit Name

Default

Bit Description

4:4

NAND Tree Mode

Internal Debug Purposes

When

set to ‘0’ places the NAND tree active

to perform the test.

To disable the NAND tree test mode this bit

should be

‘1’.

3:3

SRAM Mode

Internal Debug Purposes

When

set to ‘1’ defines the SRAM memory

test mode.

It uses the content of register 0x17 and 0x18.

2:2

Training Mode

When

set to ‘1’ defines the training test data

mode to be sent by the output LVDS data. It

uses the content of register 0x12 and 0x16.

When set to ‘0’ the Data is received from the

Pixels.

1:1

Counter Test Mode

Internal Debug Purposes

When

set to ‘1’ defines the test mode for

counter block.

0:0

ADC Test Mode

Internal Debug Purposes

When

set to ‘1’ defines the test mode for the

ADC block.

9.1.16

Training Sequence 1 Line 1 Register (Address 0x0F)

Figure 114:

TSQ1L1Reg

Address: 0x0F

Default Value: 0xFF

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Training

sequence 1

11111111b

Defines the 8 MSBs for word A training

sequence sent over the LVDS driver of Line

1 for FPGA synchronization purposes.

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