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Motore di ricerca datesheet componenti elettronici |
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AS621X Scheda tecnica(PDF) 29 Page - OSRAM GmbH |
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AS621X Scheda tecnica(HTML) 29 Page - OSRAM GmbH |
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29 / 37 page  Document Feedback AS621x Register Description Datasheet • PUBLIC DS000677 • v4-00 • 2022-May-17 36 │ 28 Figure 31: Bus Timing Specifications Parameter Symbol Fast Mode High Speed Mode Unit Min Max Min Max SCL clock frequency fSCL 0.001 0.4 0.001 3.4 MHz Bus free time between STOP and START condition tBUF 600 160 ns Hold time after repeated START condition tHDSTA 100 100 ns Repeated START condition setup time tSUSTA 100 100 ns Data in hold time tHDDAT 0 0 ns Data out hold time (1) tDH 100 100 ns Data setup time tSUDAT 100 10 ns SCL clock low period tLOW 1300 160 ns SCL clock high period tHIGH 600 60 ns Clock/Data fall time tF 300 80 ns Clock/Data rise time tR 300 80 ns Clock/Data rise time for SCL ≤100 kHz tR 1000 ns (1) The device will hold the SDA line high for 100 ns during the falling edge of the SCL. 6.3.15 Timing Diagrams The following timing diagrams depict the different bus operation modes and data transmission: |
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