DSP56F802 datasheet(13/40 Pages) FREESCALE

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JTAG/OnCE

56F802 Technical Data, Rev. 9

Freescale Semiconductor

2.8 JTAG/OnCE

Part 3 Specifications

3.1 General Characteristics

The 56F802 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The

term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology,

to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices

designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible

I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V

± 10% during

normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings

of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent

damage to the device.

Table 2-10 JTAG/On-Chip Emulation (OnCE) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

TCK

Input

(Schmitt)

Input, pulled

low internally

Test Clock Input—This input pin provides a gated clock to synchronize the

test logic and shift serial data to the JTAG/OnCE port. The pin is connected

internally to a pull-down resistor.

TMS

Input

(Schmitt)

Input, pulled

high internally

Test Mode Select Input—This input pin is used to sequence the JTAG TAP

controller’s state machine. It is sampled on the rising edge of TCK and has an

on-chip pull-up resistor.

Note:

Always tie the TMS pin to VDD through a 2.2K resistor.

TDI

Input

(Schmitt)

Input, pulled

high internally

Test Data Input—This input pin provides a serial input data stream to the

JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip

pull-up resistor.

TDO

Output

Tri-stated

Test Data Output—This tri-statable output pin provides a serial output data

stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR

controller states, and changes on the falling edge of TCK.

TRST

Input

(Schmitt)

Input, pulled

high internally

Test Reset—As an input, a low signal on this pin provides a reset signal to the

JTAG TAP controller. To ensure complete hardware reset, TRST should be

asserted at power-up and whenever RESET is asserted. The only exception

occurs in a debugging environment, since the OnCE/JTAG module is under

the control of the debugger. In this case it is not necessary to assert TRST

when asserting RESET. Outside of a debugging environment RESET should

be permanently asserted by grounding the signal, thus disabling the

OnCE/JTAG module on the device.

Note:

For normal operation, connect TRST directly to VSS. If the design is to be

used in a debugging environment, TRST may be tied to VSS through a 1K resistor.

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