56F826 datasheet(5/56 Pages) FREESCALE

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56F826 Description

56F826 Technical Data, Rev. 14

Freescale Semiconductor

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Sixteen (16) dedicated General Purpose I/O (GPIO) pins

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Thirty (30) shared General Purpose I/O (GPIO) pins

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Computer-Operating Properly (COP) Watchdog timer

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Two external interrupt pins

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External reset pin for hardware reset

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JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

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Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

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Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs

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One Time of Day module

1.1.4

Energy Information

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Dual power supply, 3.3V and 2.5V

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Wait and Multiple Stop modes available

1.2 56F826 Description

The 56F826 is a member of the 56800 core-based family of processors. It combines, on a single chip, the

processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to

create an extremely cost-effective solution for general purpose applications. Because of its low cost,

configuration flexibility, and compact program code, the 56F826 is well-suited for many applications.

The 56F826 includes many peripherals that are especially useful for applications such as: noise

suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic

alarms, POS terminals, feature phones.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming

model and optimized instruction set allow straightforward generation of efficient, compact code for both

DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable

rapid development of optimized control applications.

The 56F826 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external

dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on

peripheral configuration.

The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each

programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It

also supports program execution from external memory.

The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of

field-programmable software routines that can be used to program the main Program and Data Flash

memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page

sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.

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