PIC18(L)F23/24/43/44K22

DS80512D-page 2

 2010-2011 Microchip Technology Inc.

TABLE 2:

SILICON ISSUE SUMMARY

Module

Feature

Item

Number

Issue Summary

Affected

Revisions(1)

A1

A2

Comparators

CxSYNC Control

1.

The comparator output to the device pin

(Cx) always bypasses the Timer1

synchronization latch.

X

Clock Switching

Fail-Safe Clock Monitor

2.

When the FCMEN Configuration bit is set

and the IESO Configuration bit is not set,

then a clock failure during Sleep will not

be detected.

XX

Power-on Reset

(POR)

Power-on Reset

3.1

Transient current spikes on some parts

during power-up may cause the part to

become stuck in Reset.

X

Power-on Reset

(POR)

Power-on Reset

3.2

Min VDD for PIC18F2X/4XK22 parts is

limited to 2.3V.

Min VDD for PIC18LF2X/4XK22 parts is

1.8V.

XX

Timer1/3/5 Gate

Timer1/3/5 Gate

4.

The Timer1/3/5 gate times cannot be

resolved to the two Least Significant bits,

when using FOSC as the Timer1/3/5

source.

XX

EUSART

EUSART Asynchronous

Operation

5.

The EUSART asynchronous operation

may miss the Start bit edge.

X

Note 1:

Only those issues indicated in the last column apply to the current silicon revision.