44K22 datasheet(3/10 Pages) MICROCHIP

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DS80512D-page 3

PIC18(L)F23/24/43/44K22

Silicon Errata Issues

1. Module: Comparators

The CxSYNC controls are inoperative. The

comparator output (Cx) always bypasses the

Timer1 synchronization latch.

Work around

None.

Affected Silicon Revisions

2. Module: Clock Switching

When the FCMEN Configuration bit is set and the

IESO Configuration bit is not set, then a clock

failure during Sleep will not be detected.

Work around

The IESO Configuration bit must also be set when

the FCMEN Configuration bit is set.

Affected Silicon Revisions

3. Module: Power-on Reset (POR)

3.1

There may be transient current spikes on

some parts during power-up. If the applica-

tion cannot supply enough current to get past

these transients, then the part may become

stuck in Reset.

Work around

Ensure that the application is capable of supplying

at least 30 mA of transient current during power-

up.

Affected Silicon Revisions

3.2

Min VDD for PIC18F2X/4XK22 parts is

limited to 2.3V. Min VDD for PIC18LF2X/

4XK22 parts is 1.8V.

Work around

None.

Affected Silicon Revisions

4. Module: Timer1/3/5 Gate

The Timer gate times cannot be resolved to the

two Least Significant timer bits when the source

frequency is FOSC (TMRxCS[1:0]=01). This is

because the gate edges are synchronized with the

FOSC/4 clock.

Work around

None.

Affected Silicon Revisions

Note:

This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (A2).

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