HCS08 datasheet(167/290 Pages) MOTOROLA

167 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

167

MC9S08GB/GT

coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or

TPMxCNTL, or any write to the timer status/control register (TPMxSC).

Reset clears the TPM counter registers.

Figure 10-6 Timer x Counter Register High (TPMxCNTH)

Figure 10-7 Timer x Counter Register Low (TPMxCNTL)

When background mode is active, the timer counter and the coherency mechanism are frozen such that the

buffer latches remain in the state they were in when the background mode became active even if one or

both bytes of the counter are read while background mode is active.

10.7.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL)

The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM

counter reaches the modulo value, the TPM counter resumes counting from $0000 at the next clock

(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing

to TPMxMODH or TPMxMODL inhibits the TOF bit and overflow interrupts until the other byte is

written. Reset sets the TPM counter modulo registers to $0000 which results in a free-running timer

counter (modulo disabled).

Figure 10-8 Timer x Counter Modulo Register High (TPMxMODH)

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Any write to TPMxCNTH clears the 16-bit counter.

Reset:

00000000

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Any write to TPMxCNTL clears the 16-bit counter.

Reset:

00000000

Bit 7

654332

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

00000000

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