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HCS08 Scheda tecnica(PDF) 177 Page - Motorola, Inc |
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HCS08 Scheda tecnica(HTML) 177 Page - Motorola, Inc |
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177 / 290 page ![]() Data Sheet — MC9S08GB60/D V1.5 MOTOROLA 177 MC9S08GB/GT Figure 11-4 SCI Receiver Block Diagram The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer to 11.8.1 8- and 9-Bit Data Modes. For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode. H 8 7 6 5 4 3 2 1 0 L SCID – Rx BUFFER (READ-ONLY) INTERNAL BUS 11-BIT RECEIVE SHIFT REGISTER SHIFT DIRECTION FROM RxD PIN RATE CLOCK Rx INTERRUPT REQUEST DATA RECOVERY DIVIDE 16 × BAUD SINGLE-WIRE LOOP CONTROL WAKEUP LOGIC FROM TRANSMITTER ERROR INTERRUPT REQUEST PARITY CHECKING BY 16 RDRF RIE IDLE ILIE OR ORIE FE FEIE NF NEIE PF LOOPS PEIE PT PE RSRC WAKE ILT RWU M |
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