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MC68HC908GR4MP Scheda tecnica(PDF) 61 Page - Freescale Semiconductor, Inc |
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MC68HC908GR4MP Scheda tecnica(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 286 page  I/O Registers MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 61 ADICLK — ADC Input Clock Select Bit ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed. 1 = Internal bus clock 0 = External clock (CGMXCLK) NOTE During the conversion process, changing the ADC clock will result in an incorrect conversion. fxclk or bus frequency ADIV2–ADIV0 = 1 MHz |
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