Analog Integrated Circuit Device Data

Freescale Semiconductor

21

33982

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 10. Multiple 8-Bit Word SPI Communication

SERIAL INPUT COMMUNICATION

SPI communication is accomplished using 8-bit

messages. A message is transmitted by the MCU starting

with the MSB, D7, and ending with the LSB, D0 (Table 8).

Each incoming command message on the SI pin can be

interpreted using the following bit assignments: the MSB (D7)

is the watchdog bit and in some cases a register address bit;

the next three bits, D6:D4, are used to select the command

register; and the remaining four bits, D3:D0, are used to

configure and control the output and its protection features.

Multiple messages can be transmitted in succession to

accommodate those applications where daisy chaining is

desirable or to confirm transmitted data as long as the

messages are all multiples of eight bits. Any attempt made to

latch in a message that is not eight bits will be ignored.

The 33982B has defined registers, which are used to

configure the device and to control the state of the output.

Table 9, summarizes the SI registers. The registers are

addressed via D6:D4 of the incoming SPI word (Table 8).

CS B

SI

SC L K

D7

D1 *

D2 *

D5 *

D6 *

D7 *

D0

D1

D6

D5

D2

D0 *

OD 5

OD 6

OD 7

D6

D7

OD 0

OD 1

OD 2

D1

D2

D5

F I G U R E

4 b .

M U L T IP L E

8 b i t W O R D

S P I C O M M U N IC A T IO N

NO T E S :

D0

SO

1.

R S T B

i s

i n

a

l o gi c

1

s t at e

d u r i ng

t h e

a b o v e

op er at i o n.

2 .

D 0 , D 1 , D 2 , . . ., a n d

D 7

r e l a t e

t o

t h e

m o s t r e c e n t o r d e r e d

e n tr y o f d a ta

i n to

th e

S P S S

3.

O D 0, O D 1, O D 2, . . . , an d

O D 7

r e l a t e

t o

t h e

f i r s t 8

b i t s

o f o r de r e d

f a u l t a n d

s t a t u s

da t a

ou t o f t h e

de v i c e .

4.

O D 0, O D 1, O D 2, . . . , a n d

O D 7

r e pr e s en t t h e

f i r s t 8

bi t s

o f o r de r e d

f a u l t a n d

s t a t u s

da t a

ou t o f t h e

S P S S

CS

SCLK

SI

SO

RS T

1. RST is a Logic [1] state during the above operation.

2. D7:D0 relate to the most recent ordered entry of data into the device.

4. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.

Notes

3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.

Table 8. SI Message Bit Assignment

Bit Sig

SI Msg Bit

Message Bit Description

MSB

D7

Watchdog in: toggled to satisfy watchdog

requirements; also used as a register

address bit.

D6:D4

Register address bits.

D3:D1

Used to configure the inputs, outputs, and

the device protection features and SO

status content.

LSB

D0

Used to configure the inputs, outputs, and

the device protection features and SO

status content.