33989 datasheet(45/66 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33989

TYPICAL APPLICATIONS

SUPPLEMENTAL APPLICATION NOTES

Figure 32. Overcurrent Wake-Up

•T1:VDD1 output current deglitcher time:IDD1-DGLT: typ

55 µs

• T2: Over current detected to SBC wake-up (INT pulse)

= typ 60 µs

• The total time is 148 µs in this case.

LX with Cyclic Sense

Figure 33.

• T1: Is dependent on the selected cyclic sense timing in

the TIM2 register (5 ms to 400 ms). LX is sampled 10 µs

before the end of cyclic sense on time. If the LX correct

wake-up level happens just after sample point, the

wake-up will be detected at the next HS1 activation and

a complete period is lost.

• T2: It is the same than Lx to INT pulse: typ 100 µs

• The total time is around 5.13 ms (for a cyclic sense total

time of 5 ms) in the above example.

MC33989 CAN INTERFACE

This section is a detailed description of the CAN interface

of the MC33989.

Block Diagram

Figure 34 is a simplified block diagram of the CAN

interface of the MC33989.

INT

IDD1 current

(17 mA typ)

SBC ready to accept SPI command.

Wake-up signalled to MCU.

IDD1S-WU

tINT + tS-1STSPI (33µs max)

HS1

INT

SBC ready to accept SPI command.

Wake-up signalled to MCU.

tINT + tS-1STSPI (33µs max)

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