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MPC860DP Scheda tecnica(PDF) 22 Page - Freescale Semiconductor, Inc |
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MPC860DP Scheda tecnica(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 80 page ![]() MPC860 Family Hardware Specifications, Rev. 7 22 Freescale Semiconductor Bus Signal Timing Figure 5 provides the timing for the synchronous active pull-up and open-drain output signals. Figure 5. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing Figure 6 provides the timing for the synchronous input signals. Figure 6. Synchronous Input Signals Timing Figure 7 provides normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT TS, BB TA, BI TEA B13 B12 B11 B11a B12a B13a B15 B14 CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR B16 B17 B16a B17a B16b B17 |
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