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MPC866P Scheda tecnica(PDF) 73 Page - Freescale Semiconductor, Inc |
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MPC866P Scheda tecnica(HTML) 73 Page - Freescale Semiconductor, Inc |
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73 / 96 page ![]() MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 73 UTOPIA AC Electrical Specifications Figure 72 shows signal timings during UTOPIA receive operations. Figure 72. UTOPIA Receive Timing Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise/fall time (external clock option) Input — 4 ns Duty cycle 40 60 % Frequency — 33 MHz U2 UTPB, SOC, Rxclav and Txclav active delay Output 2 16 ns U3 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup time Input 4 — ns U4 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold time Input 1 — ns UtpClk UTPB RxEnb U1 3 2 SOC 4 RxClav PHREQn 3 4 HighZ at MPHY HighZ at MPHY U1 U2 U3 U4 U4 U3 U2 |
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