MPC8250VR datasheet(3/60 Pages) FREESCALE

3 / 60 page

MPC8250 Hardware Specifications, Rev. 1

Freescale Semiconductor

Features

— Supports bus snooping for data cache coherency

— Floating-point unit (FPU)

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Separate power supply for internal logic (1.8 V) and for I/O (3.3V)

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Separate PLLs for G2 core and for the CPM

— G2 core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

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64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

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32-bit data and 18-bit address local bus

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

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60x-to-PCI bridge

— Programmable host bridge and agent

— 32-bit data bus, 66 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

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System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

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Twelve-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-

definable peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user programmable machines, general-purpose chip-select machine, and page-mode

pipeline SDRAM machine

— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)

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