MPC8280CVRT datasheet(79/80 Pages) FREESCALE

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MPC8280 PowerQUICC II™ Family Hardware Specifications, Rev. 1.7

Freescale Semiconductor

Document Revision History

0.3

6/2003

• Removal of notes stating “no local bus” on VR-package devices. The MPC8270VR and the

MPC8275VR have local bus support.

• References to “G2 core” changed to “G2_LE core.” Refer to the

G2 Core Reference Manual

(G2CORERM/D).

• Addition of VCCSYN to “Note” below Table 4, and to note 3 of Table 5

• Figure 2: New

• Table 5: Addition of note 1

• Table 6: Addition of

θJB and θJC. Modifications to ZU package values.

• Table 7: Addition of various configurations, Modification of values. Addition of note 3.

• Table 9: Addition of 66 MHZ and 100 MHz values. Addition of sp42a/sp43a.

• Table 10: Addition of 66 MHZ and 100 MHz values

• Table 12: sp30 values. sp33b @100 MHz value. Removal of previous note 2. Modification of

current note 2.

• Figure 5, Figure 6, Figure 7, and Figure 8: Addition of notes

• Section 6.2: Addition of note on PCI timing

• Table 16, Table 17, Table 18, Table 19, Table 20: Addition of note 1 concerning minimum

operating frequencies

• Addition of statement before clock tables about selection of clock configuration and input

frequency

• Table 21 and Table 23: Addition of note 1 to CPM pins

0.2

11/2002 Table 23, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 63)

0.1

—

Initial public release

Table 25. Document Revision History (continued)

Revision

Date

Substantive Changes

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