6.3.6 Implement Output Discharge by PG function

The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage and to let

the output voltage close to 0V quickly when the device is being disabled. TPSM81033 can implement output

discharge function by PG function that requires a RDummy resistor connected between PG pin and Vout pin. PG

is an open drain NMOS architecture with up to 50mA current capability, the PG pin becomes logic high when the

output voltage reaches the target value, so the dummy load resistor does not lead any power loss during normal

operation. When the EN pin gets low, the TPSM81033 is disabled and meanwhile the PG pin gets low with a

typical 33μs glitch time (tglitch). With PG pin keeps low, the RDummy works as a dummy load to discharge output

voltage. Changing RDummy can adjust the output discharge rate.

PVIN

EN

VOUT

FB

GND

L1

OFF

ON

C1

C2

MODE

PFM

PWM

PG

R1

R2

RDummy

TPSM81033

SW

AVIN

Output

Voltage

time

PG

time

tglitch

Output voltage

discharge from RDummy

EN

Figure 6-1. Implement Output Discharge by PG function

6.3.7 Overvoltage Protection

The TPSM81033 has an output overvoltage protection (OVP) to protect the device if the external feedback

resistor divider is wrongly populated. When the output voltage is above 5.75V typically, the device stops

switching. Once the output voltage falls 0.1V below the OVP threshold, the device resumes operating again.

6.3.8 Output Short-to-Ground Protection

The TPSM81033 starts to limit the output current when the output voltage is below 1.8V. The lower the output

voltage reaches, the smaller the output current is. When the VOUT pin is short to ground, and the output voltage

becomes less than 0.4V, the output current is limited to approximately 330mA. Once the short circuit is released,

the TPSM81033 goes through the soft start-up again to the regulated output voltage.

6.3.9 Thermal Shutdown

The TPSM81033 goes into thermal shutdown once the junction temperature exceeds 170°C. When the

junction temperature drops below the thermal shutdown recovery temperature, typically 155°C, the device starts

operating again.

6.4 Device Functional Modes

TPSM81033 has two optional modes in light load by configuring the MODE pin: auto PFM mode and forced

PWM to balance the efficiency and noise immunity in light load.

6.4.1 PWM Mode

The TPSM81033 uses a quasi-constant 2.4MHz frequency pulse width modulation (PWM) at moderate to heavy

load current. Based on the input voltage to output voltage ratio, a circuit predicts the required on-time. At the

beginning of the switching cycle, the NMOS switching FET. The input voltage is applied across the inductor and

the inductor current ramps up. In this phase, the output capacitor is discharged by the load current. When the

on-time expires, the main switch NMOS FET is turned off, and the rectifier PMOS FET is turned on. The inductor

transfers its stored energy to replenish the output capacitor and supply the load. The inductor current declines

TPSM81033

SLVSHL0B – JUNE 2024 – REVISED JULY 2024

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