Data Sheet

ADN4600

Rev. C | Page 9 of 28

Figure 10 to Figure 13 were obtained using the standard test circuit shown in Figure 9.

50Ω CABLES

2

2

TP3

HIGH SPEED

SAMPLING

OSCILLOSCOPE

50Ω CABLES

2

2

50Ω

ADN4600

AC-COUPLED

EVALUATION

BOARD

INPUT

PIN

OUTPUT

PIN

PATTERN

GENERATOR

DATA OUT

TP1

50Ω CABLES

2

2

TP2

FR4 TEST BACKPLANE

DIFFERENTIAL

STRIPLINE TRACES

8mils WIDE, 8mils SPACE,

8mils DIELECTRIC HEIGHT

TRACE LENGTHS = 30''

Figure 9. Input Equalization Test Circuit, FR4 (See Figure 5 and Figure 6 for the Reference Eye Diagrams at TP1)

50ps/DIV

Figure 10. 3.25 Gbps Input Eye, 30 Inch FR4 Input Channel

(TP2 from Figure 9)

50ps/DIV

Figure 11. 4.25 Gbps Input Eye, 30 Inch FR4 Input Channel

(TP2 from Figure 9)

50ps/DIV

Figure 12. 3.25 Gbps Output Eye, 30 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 9)

50ps/DIV

Figure 13. 4.25 Gbps Output Eye, 30 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 9)