1.8V-3.3V PicoPLL

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/04/07 Page 2

KEY PROGRAMMING PARAMETERS

CLK

Output Frequency

Output Drive Strength

Programmable

Input/Output

Where M=16 bit

R= 7 bit

P= 4 bit

Three optional drive strengths to

choose from:

• Low: 4mA

• Std: 8mA (default)

• High: 16mA

One output pin can be configured as:

• OE - input

• FSEL - input

• PDB - input

• CLK1 – output

PACKAGE PIN ASSIGNMENT

Pin #

Name

SOT

Pin#

SC70

Pin#

DFN

Pin#

Type

Description

VDD

1

2

3

P

VDD connection.

OE, PDB,

FSEL, CLK1

2

1

2

I/O

This programmable I/O pin can be configured as Output Enable (OE)

input, Power Down (PDB) input, Frequency Selector (FSEL) or CLK1

clock output. This pin has an internal 10M

pull up resistor (OE, PDB &

FSEL Only).

The OE and PDB features can be programmed to allow the output

to float (Hi Z), or to operate in the ‘Active low’ mode.

State

OE

PDB

FSEL

0

Disable CLK

Power Down Mode

Frequency ‘2’

1 (default)

Normal mode

Normal mode

Frequency ‘1’

FIN

3

3

1

I

Reference input pin.

LF

4

4

6

I

Loop Filter input pin.

GND

5

5

5

P

GND connection

CLK0

6

6

4

O

Programmable Clock Output