Table 12. Receiver truth table

Differential input VID = VA-VB

ENABLE RE

OUTPUT R

Function

VTH+ < VID

L

H

Receive valid bus high

VTH- < VID < VTH+

L

I

Indeterminate bus state

VID < VTH-

L

L

Receive valid bus low

X

H

Z

Receiver disabled

X

Open

Z

Receiver disabled by default

Open-circuit bus

L

H

Fail-safe high output

Short-circuit bus

L

H

Fail-safe high output

Idle (terminated) bus

L

H

Fail-safe high output

Shutdown mode

Shutdown mode is initiated when driving DE low and RE high. In this state, the device draws less than 3.5 µA of

current in all temperature and power supply conditions. Shutdown mode is entered in typically 2 µs at VCC 5 V

and ambient temperature of 25 °C.

The ST4E1216 and ST4E1240 are designed for bidirectional data communications on multipoint bus transmission

lines. Figure 11 shows a typical network application circuit. To minimize reflections, the line should be terminated

at both ends with its characteristic impedance and stub lengths to be kept as short as possible from the main line.

Fail-safe receiver

The ST4E1216 and ST4E1240 have a fail-safe receiver to ensure a logic level on the bus and prevent any

indeterminate state. The following conditions can be detected.

•

Open bus such as a disconnected connector

•

A shorted bus such as a damaged cable creating a short of the twisted pair

•

An idle bus that occurs when no device on the bus is actively driving

In any of these cases, the differential receiver drives a fail-safe logic high level so that the output of the receiver is

not indeterminate.

Hot-swap capability

The enable pins DE and RE are critical pins during a switch-on or plug-in phase on the RS485 bus. To prevent

these pins from driving into unwanted states on the bus due to possible disturbances during these steps, the

ST4E1216 and ST4E1240 features an integrated hot-swap structure to avoid these potential problems.

Assuming a parasitic capacitance may be present on the board between the nodes DE and GND, or RE and VCC;

when the power supply rises, the MCU may drive an undetermined state on the nodes DE and RE. Depending on

the input impedance on nodes DE and RE, it can generate an unwanted signal on bus pins A, B.

A parasitic capacitance up to 100 pF is efficiently discharged with the hot-swap structure of the ST4E1216 and

ST4E1240.

The new ST RS485 transceivers manage dynamically the input impedance on DE and RE versus VCC. A typical

transient resistor of 6 kΩ is seen during the rising edge of the power supply, during a defined time of 15 µs

typically. This allows fast discharge of parasitic capacitance, preventing any unwanted signal on the bus pins. A

second typical transient resistor of 20 kΩ is still present until the VCC supply is fully established. Then, the 2 MΩ

resistors are the connected pull-up or pull-down resistor on both DE and RE terminals during normal ON

operation for current consumption considerations. An example is shown below for the impedance management on

the DE terminal. Such a structure is also present on RE versus VCC.

ST4E1216, ST4E1240

Detailed description

DS14542 - Rev 2

page 21/31