Data Sheet

AD5111/AD5113/AD5115

Rev. B | Page 9 of 24

INTERFACE TIMING SPECIFICATIONS

VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Description

f

CLK

V

DD ≥ 2.7 V

50

MHz

Clock frequency

V

DD < 2.7 V

25

MHz

t

1

25

ns

CS setup time

t

2

V

DD ≥ 2.7 V

10

ns

CLK low time

V

DD < 2.7 V

20

ns

t

3

V

DD ≥ 2.7 V

10

ns

CLK high time

V

DD < 2.7 V

20

ns

t

4

15

ns

U/D setup time

t

5

6

ns

U/D hold time

t

6

V

DD ≥ 2.7 V

20

ns

CS rise to CLK hold time

V

DD < 2.7 V

40

ns

t

7

15

ns

CS rising edge to next CLK ignored

t

8

V

DD ≥ 2.7 V

12

ns

U/D minimum pulse time

V

DD < 2.7 V

24

ns

t

9

12

ns

U/D rise to CLK falling edge

t

10

1

µs

Minimum CS time

tEEPROM_PROGRAM1

15

50

ms

Memory program time

t

POWER_UP

2

50

µs

Power-on EEPROM restore time

1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.

2 Maximum time after V

DD is equal to 2.3 V.

TIMING DIAGRAMS

t1

RWB

CLK

CS

U/D

t2

t4

t5

t6

t3

t10

t7

Figure 2. Increment/Decrement Mode Timing

DATA

EEPROM

NEW DATA

tEEPROM_PROGRAM

t1

CLK

CS

U/D

t8

t6

Figure 3. Storage Mode Timing

CS

CLK

U/D

t1

t9

t6

Figure 4. Shutdown Mode Timing