24LC174-SLASHP datasheet(6/14 Pages) MICROCHIP

6 / 14 page

24LC174

DS21101H-page 6

 2004 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

SDA LINE

DATA

CONTROL

BYTE

WORD

ADDRESS

BUS ACTIVITY:

MASTER

BUS ACTIVITY:

1 A2

A1 A0 B2 B1

SDA LINE

DATA n

CONTROL

BYTE

WORD

ADDRESS (n)

BUS ACTIVITY:

MASTER

BUS ACTIVITY:

DATA n + 1

DATA n + 15

A1 A0 B2 B1

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for flow diagram.

FIGURE 5-1:

ACKNOWLEDGE POLLING

FLOW

6.0

WRITE PROTECTION

The 24LC174 can be used as a serial ROM when the

WP pin is connected to Vcc. Programming will be inhib-

ited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

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