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STM32F101C6 Scheda tecnica(PDF) 56 Page - STMicroelectronics |
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STM32F101C6 Scheda tecnica(HTML) 56 Page - STMicroelectronics |
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56 / 64 page ![]() Electrical characteristics STM32F101xx 56/64 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 23 or Figure 24, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 23. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF- inputs are available only on 100-pin packages. Figure 24. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF- inputs are available only on 100-pin packages. V REF+ STM32F101xx V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai14380 VREF+/VDDA STM32F101xx 1 µF // 10 nF VREF–/VSSA ai14380 |
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