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SPSB100 Scheda tecnica(PDF) 124 Page - STMicroelectronics |
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SPSB100 Scheda tecnica(HTML) 124 Page - STMicroelectronics |
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124 / 214 page ![]() Table 72. DCR3 (0x03) MSB description Bit Name Description 23 RES Reserved 22 RES Reserved 21 BUCK3_SPREAD_ENA Frequency spread selection 1: Enabled 0: Disabled (default) 20 BUCK2_SPREAD_ENA Frequency spread selection 1: Enabled 0: Disabled (default) 19 BUCK1_SPREAD_ENA Frequency spread selection 1: Enabled 0: Disabled (default) 18 CLR_WDFAIL_CNT Clear WDFAIL_CNT to 0 This bit is always read low 17 RES Reserved 16 BUCK3_FTUNE_2 Table 73. DCR3 (0x03) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 (R/W) 1 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) BUCK3_FTUNE_1 BUCK3_FTUNE_0 BOOST_OFF FBB_OV_EW_TH_3 FBB_OV_EW_TH_2 FBB_OV_EW_TH_1 FBB_OV_EW_TH_0 FBB_UV_EW_TH_3 BUCK3 fine-tune bit 1 BUCK3 fine-tune bit 0 BOOST disable bit FBB overvoltage early warning threshold bit 3 FBB overvoltage early warning threshold bit 2 FBB overvoltage early warning threshold bit 1 FBB overvoltage early warning threshold bit 0 FBB undervoltage early warning threshold bit 3 Table 74. DCR3 (0x03) description Bit Name Description 15 BUCK3_FTUNE_1 14 BUCK3_FTUNE_0 Valid only if U-NVM bits BUCK3_PU_VALUE = 001 11x: 0.95 V 101: 0.96 V 100: 0.97 V 000: 0.98 V (default) 001: 0.99 V 010: 1.00 V 011: 1.01 V 13 BOOST_OFF Boost disable 1: Boost is disabled 0: Boost feature define by BOOST_DIS U-NVM bit (default) 12 FBB_OV_EW_TH_3 FBB over voltage early warning threshold At FBB > FBB_OV_EW_TH, an interrupt is generated on IRQ pin and status bit FBB_OV_EW in SR4 is set (in active mode) 0000: (default) feature deactivated 0001: 17 V ... (1 V step) SPSB100 SPI registers DS14640 - Rev 1 page 124/214 |
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