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SPSB100 Scheda tecnica(PDF) 135 Page - STMicroelectronics |
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SPSB100 Scheda tecnica(HTML) 135 Page - STMicroelectronics |
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135 / 214 page ![]() Table 105. DCR8 (0x08) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R/W) 0 (R/W) 1 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) RES RES RES GO_INIT CRC3 CRC2 CRC1 CRC0 Reserved Reserved Reserved NVM init bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 106. DCR8 (0x08) LSB description Bit Name Description 7 RES Reserved 6 RES Reserved 5 RES Reserved 4 GO_INIT 1: NVM emulation and load phases are completed and INIT state can be executed (valid only in USER_NVM_PROG state) This bit is automatically cleared and always read low and always read low 0: (default) 3 CRC3 2 CRC2 1 CRC1 0 CRC0 SPSB100 SPI registers DS14640 - Rev 1 page 135/214 |
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