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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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SPSB100 Scheda tecnica(PDF) 133 Page - STMicroelectronics |
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SPSB100 Scheda tecnica(HTML) 133 Page - STMicroelectronics |
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133 / 214 page  Bit Name Description 9 MASK_CL0_TW_IRQ 1: IRQ masked 0: IRQ not masked 8 MASK_OUTHS_IRQ 1: IRQ masked 0: IRQ not masked Table 99. DCR7 (0x07) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) MASK_SPI_ERROR_IRQ MASK_NFSO1_ECHO_ERROR_IRQ MASK_WD_ENA_ECHO_ERROR_IRQ MASK_FCCU_ENA_ECHO_ERROR_IRQ CRC3 CRC2 CRC1 CRC0 Mask SPI error interrupt bit Mask NFSO1 echo error interrupt bit Mask watchdog enable echo error interrupt bit Mask FCCU enable echo error interrupt bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 100. DCR7 (0x07) LSB description Bit Name Description 7 MASK_SPI_ERROR_IRQ 1: IRQ masked 0: IRQ not masked 6 MASK_NFSO1_ECHO_ERROR_IRQ 1: IRQ masked 0: IRQ not masked 5 MASK_WD_ENA_ECHO_ERROR_IRQ 1: IRQ masked 0: IRQ not masked 4 MASK_FCCU_ENA_ECHO_ERROR_IRQ 1: IRQ masked 0: IRQ not masked 3 CRC3 2 CRC2 1 CRC1 0 CRC0 Table 101. DCR8 (0x08) MSB Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 - (R0) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) RES MASK_SWDBG_VIO_IRQ MASK_LP_READY_IRQ CLR_TSD_CNT_FAIL MASK_BUCK3_OC_POWER_OFF MASK_BUCK2_OC_POWER_OFF MASK_BUCK1_OC_POWER_OFF MASK_BUCK3_UV_POWER_OFF Reserved Mask software debug VIO interrupt bit Mask low power mode ready interrupt bit Clear TSD_CNT_FAIL bit Mask BUCK3 overcurrent power off bit Mask BUCK2 overcurrent power off bit Mask BUCK1 overcurrent power off bit Mask BUCK3 undervoltage power off bit Table 102. DCR8 (0x08) MSB description Bit Name Description 23 RES reserved 22 MASK_SWDBG_VIO_IRQ Mask IRQ when SWDBG is still at VIO at the end of timeout detection. In this case, watchdog is restarted with a long open window and SWDBG is ignored. 1: IRQ is masked 0: IRQ not masked 21 MASK_LP_READY_IRQ Mask IRQ when FSM goes to low power state. 1: IRQ is masked 0: IRQ not masked 20 CLR_TSD_CNT_FAIL Clear TSD_CNT_FAIL to 0 This bit is always read low SPSB100 SPI registers DS14640 - Rev 1 page 133/214 |
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