3

Functional description

3.1

Interfaces

3.1.1

Inter-integrated circuit (I²C)

The VD66GY is configured and controlled via an I²C interface operating in either fast mode (up to 400 kHz) or fast

mode plus (up to 1 MHz) at 1.8 V. After the MCU boot sequence, the default I²C configuration is fast mode plus

with a sink capability set to 20 mA. Drive capability can be decreased to 4 mA (fast mode) by writing a dedicated

register once the system has booted. Device addressing uses a CCI protocol with 2 byte subaddresses. The

default sensor address is 0x20 (including R/W bit), and can be overridden:

•

Permanently by storing a non-null value in a dedicated OTP register.

•

Dynamically with a firmware command when the MCU state is SW_STANDBY.

3.1.2

Camera serial interface (CSI)

The sensor is ready to connect via a dual lane mobile industry processor interface (MIPI) CSI-2 serial interface.

The dual lane MIPI CSI-2 serial interface supports up to 1.5 Gbps per lane. It is the industry standard for low

electromagnetic interference (EMI) and excellent electromagnetic compatibility (EMC) high-speed interfacing. The

CSI lane number can be lowered to a single lane. Resolution is scalable between RAW8 and RAW10.

3.2

Power supplies

The power supplies required by the sensor are:

•

2.8 V for the analog blocks

•

1.8 V for the digital I/Os

•

1.15 V for the core digital logic and MIPI CSI-2 output drivers

The pixel array requires different positive and negative voltages, all internally generated by charge pumps and

regulators. Four voltage references, internally generated, need external decoupling capacitors. The internal MCU

handles the entire power management of the sensor to guarantee the lowest power consumption at any given

time.

3.3

Clock and PLL

An input clock is required from an external digital clock source in the range of 6 to 27 MHz. Firmware is

preconfigured for a 12 MHz external source clock. Two built-in PLL (phase-locked loop) blocks generate all

necessary internal clocks for the pixel array, processing pipe, and output interface.

VD66GY

Functional description

DS13838 - Rev 7

page 5/37