AD9858SLASHPCBZ datasheet(18/32 Pages) AD

18 / 32 page

AD9858

Rev. C | Page 18 of 32

A DFRRW value of 0 written to the register stops all frequency

sweeping. There is no automated stop-at-a-given-frequency

function. The user must calculate the time interval required to

reach the final frequency and then issue a command to write 0

into the DFRRW register. The time required for a frequency

sweep is calculated by

DFTW

DFRRW

SYSCLK

−

where:

T is the duration of the sweep in seconds.

fS is the starting frequency determined by

SYSCLK

FTW

fF is the final frequency.

The delta frequency step size is given by

SYSCLK

DFTW ×

Δf

remembering that DFTW is a signed (twos complement) value.

The time between each frequency step (Δt) is given by

SYSCLK

DFRRW

= 8

Δt

The value of the stop frequency fF is determined by

Δt

Δf

Returning to Starting Frequency

The original frequency tuning word (FTW), which is written into

the frequency tuning register, does not change at any time during

a sweep operation. This means that the DDS can return to the

sweep starting frequency at any time during a sweep. Setting the

control bit, autoclear frequency accumulator, forces the frequency

accumulator to 0, instantly returning the DDS to the frequency

stored as FTW.

Full Sleep Mode

Setting all of the power-down bits in the control function register

activates full sleep mode. During the power-down condition,

the clocks associated with the various functional blocks of the

device are turned off, thereby offering a significant power savings.

SYNCHRONIZATION

SYNCLK and FUD Pins

Timing for the AD9858 is provided via the user-supplied REFCLK

input. The REFCLK input is buffered and is the source for the

internally generated SYSCLK. The frequency of SYSCLK can be

either the same as REFCLK or half that of REFCLK (CFR[6]).

The REFCLK input is capable of handling input frequencies as

high as 2 GHz. However, the device is designed for a maximum

SYSCLK frequency of 1 GHz. Thus, it is mandatory that the

divide-by-2 SYSCLK function be enabled when the frequency

of REFCLK is greater than 1 GHz.

SYSCLK serves as the sample clock for the DAC and is fed to

a divide-by-8 frequency divider to produce SYNCLK. SYNCLK

is provided to the user on the SYNCLK pin. This enables

synchronization of external hardware with the internal DDS

clock of the AD9858. External hardware that is synchronized

to the SYNCLK signal can then be used to provide the frequency

update (FUD) signal to the AD9858. The FUD signal and

SYNCLK are used to transfer the internal buffer register

contents into the memory registers of the device. Figure 33

shows a block diagram of the synchronization methodology,

and Figure 34 shows an I/O synchronization timing diagram.

SYNCLK is also used to synchronize the assertion of the profile

select pins (PS0 and PS1). The FUD, PS0, and PS1 pins must be

set up and held around the rising edge of SYNCLK.

MEMORY

EDGE

DETECTION

LOGIC

REFCLK

PS0, PS1

FUD

SYNCLK

SYSCLK

2 GHz DIVIDER

DISABLE

SYNCLK

DISABLE

TO CORE LOGIC

BUFFER

MEMORY

÷ 2

WR/SCLK

ADDRx

DATA

SYNCLK

÷ 8

Figure 33. I/O Synchronization Block Diagram

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