AD9858

Rev. C | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

84

83

82

81

80

79

78

77

76

95

94

93

92

91

90

89

88

87

86

85

100

999897

96

26

28

29

30

31

32

33

38

39

34

35

36

37

42

40

41

43

44

45

46

47

48

49

50

13

DVDD

D7

D6

D5

D4

DGND

DGND

DVDD

DVDD

D3

D2

D1

D0

ADDR5

ADDR4

ADDR3

RD/CS

DVDD

DVDD

ADDR2/IORESET

ADDR1/SDO

ADDR0/SDIO

WR/SCLK

DVDD

DGND

AVDD

NC

AGND

AVDD

DIV

DIV

AVDD

AGND

CPGND

CPVDD

CP

CP

CPFL

CPGND

CPVDD

CPISET

RF

RF

AGND

NC

NC

PFD

PFD

IF

IF

AD9858

TOP VIEW

(Not to Scale)

27

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

NOTES

1. NC = NO CONNECT.

2. THE TQFP_EP (THERMAL SLUG) MUST BE ATTACHED TO THE GROUND PLANE OR SOME OTHER LARGE

METAL MASS FOR THERMAL TRANSFER. FAILURE TO DO SO MAY CAUSE EXCESSIVE DIE TEMPERATURE

RISE AND DAMAGE TO THE DEVICE.

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

I/O

Description

1 to 4, 9 to 12

D7 to D0

I

Parallel Port Data. The functionality of these pins is valid only when the I/O port is configured as

a parallel port.

5, 6, 21, 28, 95, 96

DGND

Digitial Ground.

7, 8, 20, 23 to 27,

93, 94

DVDD

Digital Supply Voltage.

13 to 18

ADDR5 to

ADDR0

I

When the I/O port is configured as a parallel port, these pins serve as a 6-bit address select for

accessing the on-chip registers (see the IORESET, SDO, and SDIO pins for the serial port mode).

16

IORESET

I

This is valid for serial programming mode only. Active high input signal that resets the serial I/O

bus controller. It serves as a means of recovering from an unresponsive serial bus caused by

an improper programming protocol. Asserting an I/O reset does not affect the contents of

previously programmed registers, nor does it invoke their default values.