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AD9913

Data Sheet

Rev. E | Page 18 of 32

CLOCK INPUT (REF_CLK)

REF_CLK OVERVIEW

The AD9913 supports a number of options for producing the

internal SYSCLK signal (that is, the DAC sample clock) via the

REF_CLK input pins. The REF_CLK input can be driven

directly from a differential or single-ended source, or it can

accept a crystal connected across the two input pins. There is

also an internal phase-locked loop (PLL) multiplier that can be

independently enabled. The various input configurations are

controlled by means of the control bits in the CFR2 [7:5]

Table 6. Clock Input Mode Configuration

CFR2 [7:5]

Mode Configuration

000

Differential Input, PLL Enabled

001

Differential Input, PLL Disabled (Default)

x101

XTAL Input, PLL Enabled

x111

XTAL Input, PLL Disabled

100

CMOS Input, PLL Enabled

101

CMOS Input PLL Disabled

1 x = don’t care.

XTAL

REF_CLK

CMOS

÷2

PLL

CFR2[5]

CFR2[6]

CFR2[5:0]

CFR2[14:9]

DIFFERENTIAL/

SINGLE

CFR2[15]

CFR2[3]

CFR2[7:6]

SYSTEM

CLOCK

Figure 26. Internal Clock Path Functional Block Diagram

CRYSTAL-DRIVEN REF_CLK

When using a crystal at the REF_CLK input, the resonant

frequency should be approximately 25 MHz. Figure 27 shows

the recommended circuit configuration.

REFCLK

39pF

XTAL

Figure 27. Crystal Connection Diagram

DIRECT-DRIVEN REF_CLK

When driving the REF_CLK inputs directly from a signal

source, either single-ended or differential signals can be used.

With a differential signal source, the REF_CLK pins are driven

with complementary signals and ac-coupled with 0.1 μF

capacitors. With a single-ended signal source, either a single-

ended-to-differential conversion can be employed or the

REF_CLK input can be driven single-ended directly. In either

case, 0.1 μF capacitors are used to ac couple both REF_CLK

pins to avoid disturbing the internal dc bias voltage of ~1.35 V.

See Figure 28 for more details.

The REF_CLK input resistance is ~2.7 kΩ differential (~1.35 kΩ

single-ended). Most signal sources have relatively low output

impedances. The REF_CLK input resistance is relatively high,

therefore, its effect on the termination impedance is negligible

and can usually be chosen to be the same as the output imped-

ance of the signal source. The bottom two examples in Figure

28 assume a signal source with a 50 Ω output impedance.

TERMINATION

REF_CLK

DIFFERENTIAL SOURCE,

DIFFERENTIAL INPUT

SINGLE-ENDED SOURCE,

DIFFERENTIAL INPUT

SINGLE-ENDED SOURCE,

SINGLE-ENDED INPUT

0.1µF

LVPECL,

LVDS

DRIVER

REF_CLK

50Ω

0.1µF

BALUN

(1:1)

REF_CLK

0.1µF

50Ω

Figure 28. Direct Connection Diagram

CMOS-DRIVEN REF_CLK

This mode is enabled by writing CFR2 [7] to be true. In this

state, the AD9913 must be driven at Pin 13 with the reference

clock source. Additionally, it is recommended that Pin 14 in

CMOS mode be tied to ground through a 10 kΩ resistor.

REF_CLK

10kΩ

CMOS

DRIVER

Figure 29. CMOS-Driven Diagram

PHASE-LOCKED LOOP (PLL) MULTIPLIER

An internal phase-locked loop (PLL) provides users of the

AD9913 the option to use a reference clock frequency that is

lower than the system clock frequency. The PLL supports a wide

range of programmable frequency multiplication factors (1× to

64×). See Table 7 for details on configuring the PLL multipli-

cation factor. The PLL is also equipped with a PLL_LOCK bit.

CFR2 [15:8] and CFR2 [5:1] control the PLL operation. Upon

power-up, the PLL is off. To initialize the PLL, CFR2 [5] must

be cleared and CFR2 [1] must be set. The function of CFR2 [1]

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