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ST7LITE49M Scheda tecnica(PDF) 187 Page - STMicroelectronics |
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ST7LITE49M Scheda tecnica(HTML) 187 Page - STMicroelectronics |
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187 / 188 page  ST7LITE49M Revision history 187/188 16 Revision history Table 106. Document revision history Date Revision Changes 01-Jun-2007 1 Initial release. 13-July-2007 2 Document reformatted and status updated to Full Datasheet. Table 5. EEPROM register mapping and reset values removed. Section 7.2.3: Internal RC oscillator updated. Section 7.5.3: AVD Threshold Selection register (AVDTHCR): global description of AVD[1:0] added. Table 69: Operating characteristics with LVD: IDD(LVD) typical and maximum values updated, and note removed; VtPOR minimum value updated. Table 71: Voltage drop: minimum and maximum values added. Table 72: Internal RC oscillator characteristics (5.0 V calibration), Table 73: Internal RC oscillator characteristics (3.3 V calibration), and Table 74: Supply current characteristics updated. Figure 67, Figure 68, Figure 69,Figure 71, and Figure 76 updated. Table 75: On-chip peripheral characteristics values and Note 2 updated. tprog and NRW updated in Table 83: Flash program memory characteristics. NRW updated in Table 84: Data EEPROM memory characteristics. Class updated forVFESD in Table 85: EMS characteristics. Table 86: EMI characteristics updated. Table 86: EMI characteristics updated. RPU and RON updated in Table 89: General characteristics and Table 91: Asynchronous RESET pin characteristics, respectively. |
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