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ADAU1961WBCPZ-R7 Scheda tecnica(PDF) 23 Page - Analog Devices

Il numero della parte ADAU1961WBCPZ-R7
Spiegazioni elettronici  Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  73 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADAU1961WBCPZ-R7 Scheda tecnica(HTML) 23 Page - Analog Devices

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Data Sheet
ADAU1961
STARTUP, INITIALIZATION, AND POWER
analog.com
Rev. B | 23 of 73
clock for reading and writing, do not attempt to access any other
register. Any read or write is prohibited until the core clock enable
bit (COREN) and the lock bit are both asserted.
To program the PLL during initialization or reconfiguration of the
clock setting, the following procedure must be followed:
1. Power down the PLL.
2. Reset the PLL control register.
3. Start the PLL.
4. Poll the lock bit.
5. Assert the core clock enable bit after the PLL lock is acquired.
The PLL control register (Register R1, Address 0x4002) is a 48-bit
register where all bits must be written with a single continuous write
to the control port.



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