TDA8763MSLASH3 datasheet(10/24 Pages) PHILIPS

10 / 24 page

1999 Jan 06

Philips Semiconductors

Product speciﬁcation

10-bit high-speed low-power ADC with

internal reference regulator

TDA8763

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 0.5 ns.

2. Analog input voltages producing code 0 up to and including code 1023:

a) Voffset(B) (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00

and the reference voltage BOTTOM (VRB) at Tamb =25 °C.

b) Voffset(T) (voltage offset TOP) is the difference between reference voltage TOP (VRT) and the analog input which

produces data outputs equal to code 1023 at Tamb =25 °C.

TWO-TONE; note 8

TTIR

two-tone intermodulation

rejection

fclk = 40 MHz

−−69

−

BIT ERROR RATE

BER

bit error rate

fclk = 50 MHz;

fi = 4.43 MHz;

VI = ±16 LSB at code 512

−

10−13

−

times/

sample

DIFFERENTIAL GAIN; note 9

Gdiff

differential gain

fclk = 40 MHz;

PAL modulated ramp

−

0.8

−

DIFFERENTIAL PHASE; note 9

diff

differential phase

fclk = 40 MHz;

PAL modulated ramp

−

0.4

−

deg

Timing (fclk = 40 MHz; CL = 15 pF); see Fig.4; note 10

tds

sampling delay time

−

output hold time

−−

output delay time

VCCO = 4.75 V

−

VCCO = 3.15 V

−

digital output load capacitance

−−

3-state output delay times; see Fig.5

tdZH

enable HIGH

−

5.5

8.5

tdZL

enable LOW

−

tdHZ

disable HIGH

−

tdLZ

disable LOW

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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