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ADBMS2950BCCSZ Scheda tecnica(PDF) 8 Page - Analog Devices |
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ADBMS2950BCCSZ Scheda tecnica(HTML) 8 Page - Analog Devices |
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8 / 97 page  ADBMS2950B Data Sheet Rev. 0 | Page 8 of 97 OTHER ELECTRICAL SPECIFICATIONS Operating junction temperature (TJ) = −40°C to +125°C, VDD = 12V, VREG = 5.0V, ISOMD pin is connected low, unless otherwise noted. Table 8. General Timing Specifications Parameter Min Typ Max Unit Test Conditions/Comments OSCILLATOR FREQUENCIES OSC1 Frequency fOSC1 1.87 2.07 2.27 MHz OSC2 Frequency fOSC2 8.28 kHz OSC3 Frequency fOSC3 100 kHz STARTUP TIMINGS Regulator Startup (tWAKE) 200 500 µs VREG generated from DRIVE pin, time after VDD exceeds VDRUV threshold Reference Startup (tREFUP) 3.5 4.5 ms Time required to transition into REFUP after power-up or SRST IxADC Startup (tIxADC_STARTUP) 8.1 9 9.9 ms Time required for the first IxADC result to be available after receiving an ADIx command within the REFUP state for the first time after power-up or SRST IxADC Initialization (tIxADC_INIT) 115 127 140 ms Time required for the IxADCs to initialize after tIxADC_STARTUP expiry Table 9. General-Purpose Outputs Parameter Min Typ Max Unit Test Conditions/Comments Low-Level Output Voltage 0.4 V IGPOX = 1 mA High-Level Output Voltage VDD − 0.5 V IGPOX = −1 mA Low-Level Readback Threshold 0.6 1.3 V High-Level Readback Threshold VDD − 1.3 VDD − 0.6 V IGPOX = −1 mA GPO6 Output Frequency 186 207 228 kHz GPO6C = 0b10 GPO6 Output Duty Cycle 49 50 51 % GPO6C = 0b10, push-pull output enabled, external capacitance ≤ 200 pF Rise Time 1 µs CL = 200 pF Fall Time 1 µs CL = 200 pF Leakage Current −10 2.5 +10 μA Both low-side and high-side drivers disabled Table 10. General-Purpose Input/Open Drain Outputs Parameter Min Typ Max Unit Test Conditions/Comments Low-Level Output Voltage 0.3 V IGPIOX = 4 mA Input Threshold 0.8 2.3 V Leakage Current 1 μA Pin voltage = 5V, pin not asserted logic low Table 11. OC Outputs Parameter Min Typ Max Unit Test Conditions/Comments Low-Level Output Voltage 0.4 V IOCX = 10 mA High-Level Output Voltage VREG − 0.4 V IOCX = −10 mA Readback-Input Threshold Voltage 1.2 3 V PWM Output Frequency 14.4 16 17.9 kHz PWM1 or PWM2 mode selected PWM Duty-Cycle Absolute Error −1 +1 % PWM1 or PWM2 mode selected, push-pull output enabled, external capacitance ≤ 200 pF Leakage Current −10 +10 μA Both low-side and high-side drivers disabled Table 12. General DC Specifications Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE VDD Supply Voltage VDD Range 1 4.5 5.5 V DRIVE output low VDD Range 2 11 20 V DRIVE output enabled VREG Supply Voltage 4.5 5 5.5 V DRIVE PIN Output Voltage 5.5 5.7 5.9 V TA = 25°C, ILOAD = 2 mA, VDD ≥ 11V Output Current −0.2 +5 mA ΔVDRIVE < ±100 mV Temperature Coefficient −1.6 mV/°C SUPPLY CURRENT VDD Supply Current Excluding GPO sourcing current 4.5 ≤ VDD ≤ 5.5V 0.06 mA VDD ≥ 11V 0.1 mA Also excluding DRIVE output current VREG Supply Current Excluding OC and VREF1P25 sourcing current REFUP (OCEN = 0) 3.9 mA REFUP (OCEN = 1) 4.3 mA REFUP + OC ADCs active MEASURE 16.3 19.5 mA REFUP + all ADCs active |
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